library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- This module outputs input + 4
entity one_adder is
generic (N : integer :=32);
port(	data_in  : in  std_logic_vector (N-1 downto 0);
		data_out : out std_logic_vector (N-1 downto 0)
);
end one_adder;

architecture Behavioral of one_adder is
begin

data_out <= std_logic_vector(unsigned(data_in) + 1);

end Behavioral;

